Field of the Invention
The lies in the electronics field. Specifically, the present invention relates to a circuit configuration for producing complementary signals, in which an input signal that is present at an input terminal is routed on a first path to a first output terminal via a pass element and on a second path, connected in parallel with the first path, to a second output terminal via an inverter.
In this context, a pass element should be understood as meaning an element with an input and an output, such as, in particular, a transfer gate or else a switch. By way of example, such a pass element can comprise a parallel circuit made up of an n-channel MOS transistor and a p-channel MOS transistor whose sources and drains are connected to one another in each case and whose gates are driven by mutually inverted signals, so that the pass element is either on or off depending on the control signal.
An existing circuit configuration of the type mentioned in the introduction thus has a pass element in the first path and an inverter in the second path, connected in parallel with the latter, so that the pass element and the inverter are used to obtain mutually complementary signals from one input signal.
Such a circuit configuration is quite simple in its layout since it requires only one inverter and one pass element to provide the complementary output signals. For time-critical applications, however, the existing circuit configuration has a significant disadvantage: the delays which the signals experience through the pass element and the inverter differ from one another to a significant extent as a result of the process. The time difference, resulting from the process window, between the mutually complementary signals cannot be eliminated in practice, which is extremely undesirable for the time-critical applications mentioned, such as in a DLL (delayed locked loop). This means that the existing circuit configurations comprising an inverter and a pass element cannot be used satisfactorily for high-precision applications.
Referring now to FIG. 2 of the drawing, there is shown a prior art circuit configuration with an inverter 1 and a pass element 2 comprising a p-channel MOS transistor 3 and an n-channel MOS transistor 4. The transistors 3 and 4 are interconnected by their source and drain in each case and are thus connected in parallel with one another. The gates of the transistors 3, 4 have the fixed potentials of the supply voltages VSS and VDD, respectively, applied to them.
An input signal IN is received at an input terminal 5. The signal travels via an inverter 1 to a first output terminal 6 and to a second output terminal 7 via the pass element 2. On account of the various delays, resulting from the process window, caused by the inverter 1 and the pass element 2, respectively, signals C1 and C2, respectively, at the output terminals 6 and 7 are therefore not in sync, but have a considerable time difference in respect of one another. The time difference is extremely disadvantageous for time-critical applications such as a DLL.